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(R)
FC106
Fibre Channel Transceiver 1.0625 GBaud
PRELIMINARY DATA
FEATURES
s
Serial Link Transceiver
q q
serializer and deserializer implementing the Fibre Channel FC0 and FC1 layers
Parallel Interface
Receive Byte Clock
REFCLK
10 bits
s
s
s s
Direct support for 1.0625 GBaud Fibre Channel (ANSI X3.230-1994) rates Fibre Channel 10-bit Interface (ANSI TR/X3.18-199X) Direct interfaces to optical tranceivers Plesiochronous mode operation
q
8 bit / 10 bit DECODER (optional)
8 bit / 10 bit ENCODER (optional)
transmitter and receiver clock frequencies may differ by up to 100 ppm
DESER IALIZER CLOCK RECOVERY BYTE AND WORD ALIGNEMENT
s
s
s
s s s
s s s
s
Integrated Fibre Channel 8b/10b encode/decode (optional use through JTAG) Byte and word synchronization of incoming serial stream Supports any DC-balanced encoding scheme Internal Loop-Back for Self-Test Random Pattern Auto-Test Optional integrated impedance adaptation to transmission line characteristics (50 or 75 ohms) TTL compatible parallel I/O's JTAG Test Access Port 0.35 CMOS Technology for low cost and low power PQFP package available in two sizes: 14x14 mm (FC106/14) or 10x10 mm (FC106/10)
SERIALI ZER AND CLOCK FREQUENCY MULTIPLICATION
FC 106
1.0625 Gbaud Serial data over copper or optical cables
APPLICATIONS
s s s
s
Fibre Channel Arbitrated Loop Fibre Channel fabric Transmission schemes encoding bytes as 10-bit characters to form a DC-balanced stream High performance backplane interconnect
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FC106
Table of Contents
1 2 3 General Description - - - - - - - - - - - - - - - - - - - - - - 4 Interface Diagram - - - - - - - - - - - - - - - - - - - - - - - 6 Functional Description - - - - - - - - - - - - - - - - - - - - 7 3.1 Block diagram - - - - - - - - - - - - - - - - - - - - - - - 8 3.2 Input latches - - - - - - - - - - - - - - - - - - - - - - - - 8 3.3 8bit/10bit Encoder/Decoder - - - - - - - - - - - - - - - - - 9 3.4 DLL clock generator - - - - - - - - - - - - - - - - - - - - 9 3.5 Serializer functional description and reference clock - - - - - 9 3.6 Serializer latches and XOR-tree - - - - - - - - - - - - - - 10 3.7 Serial input multiplexer - - - - - - - - - - - - - - - - - - 10 3.8 Deserializer functional description - - - - - - - - - - - - - 10 3.9 Bit alignment - - - - - - - - - - - - - - - - - - - - - - - 11 3.10 Byte and word alignment - - - - - - - - - - - - - - - - 12
3.11 Clock recovery - - - - - - - - - - - - - - - - - - - - - 12 3.12 Serial input-output buffer - - - - - - - - - - - - - - - - 13
3.13 I/O impedance control - - - - - - - - - - - - - - - - - - 14 3.14 Self-test - - - - - - - - - - - - - - - - - - - - - - - - - 15 4 5 Serial I/O Electrical Model - - - - - - - - - - - - - - - - - 16
Electrical Specifications - - - - - - - - - - - - - - - - - - 17 5.1 Absolute maximum ratings - - - - - - - - - - - - - - - - 17 5.2 Operating conditions - - - - - - - - - - - - - - - - - - - 17 5.3 DC characteristics - - - - - - - - - - - - - - - - - - - - 18
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FC106 6 Timing Specifications - - - - - - - - - - - - - - - - - - - - 20 6.1 Transmit interface timing and latency - - - - - - - - - - - 20 6.2 Receive interface timing - - - - - - - - - - - - - - - - - 21 6.2.1 Receive clock timing and latency - - - - - - - - - - - 21 6.2.2 Receive interface timing - - - - - - - - - - - - - - - 23 6.3 Serial Input/output AC characteristics - - - - - - - - - - - 24 7 FC106 Pin Description - - - - - - - - - - - - - - - - - - - 25 7.1 Pin summary - - - - - - - - - - - - - - - - - - - - - - - 25 7.2 Pin functions - - - - - - - - - - - - - - - - - - - - - - - 26 8 Package Specifications - - - - - - - - - - - - - - - - - - - 29 8.1 FC106 64-pin PQFP pinout - - - - - - - - - - - - - - - - 29 8.2 FC106 64-pin Quad Flat-pack package dimensions - - - - 30 8.2.1 FC106/14: 14x14 mm package dimensions - - - - - - 30 8.2.2 FC106/10: 10x10 mm package dimensions - - - - - - 31
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FC106
1
General Description
The FC106 Fibre Channel transceiver chip implements the lower layer protocols of the ANSI X3.230-1994 Fibre Channel standard. The Fibre Channel standard specifies the mapping of various upper layer protocols (ULP) such as SCSI, IP and HiPPI to a common lower layer protocol, together with appropriate electrical and optical high performance specifications. Fibre Channel provides a channel over which concurrent communication of a variety of ULP's may exist on a single interconnect between workstations, mainframes and supercomputers, and provides a connection to mass storage devices and other peripherals. The FC106 implements the Fibre Channel electrical transceiver physical layer specification for 1.0625 Gbit/s. At this frequency, the Fibre Channel delivers 100 MByte/s of data bandwidth over a twin coaxial or twin optical fibre cable. This bandwidth equals or exceeds most bus bandwidths. The FC106 chip performs the high speed serialization and deserialization function that makes bus-bandwidth, serial communication possible. This chip can drive electrical cables directly or it can interface with suitable optical modules. Figure 1.1 shows the different connections. Figure 1.1 FC106 chip connections
1.0625 Gb/s
System 1
Serial Data over copper or optical cables
System 2
REFCLK (1)
REFCLK (2)
Fibre
Fibre
I/O Bus
Channel Controll er
FC106
FC106
Channel Controller
The parallel interface on the FC106 is compatible with the 10-Bit Interface Specification (ANSI TR/X3.18-1998) which defines a common, standard signaling interface between the Fibre Channel Physical and Protocol layers. In addition, the FC106 can be used for all other proprietary serial links transmitting data as 10-bit encoded characters. The FC106 incorporates an impedance adaptor circuit (set by the pins ZC+, ZC-) to ensure high quality adaptation to the transmission line characteristic impedance.This feature is optional and the user can keep external adaptation for compatibility reasons.
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I/O Bus
10 bits
10 bits
FC106
The FC106 integrates a loop-back path for system-level test purposes. It also includes a self-test capability in which random patterns are transmitted through the internal loop-back path and compared after reception. The FC106 is implemented in a standard digital 0.35 CMOS process. Its typical power consumption is 0.4 Watts (not including the power required to drive the TTL parallel output port, which is in the 0.1 Watt range for output capacitive loads of 10 pF per pin).
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FC106
2
Interface Diagram
Interface diagram TTTTT T C R MD D R A E K S S I OS T N
Figure 2.1
Test 10 FC Protocol Device TX[0:9] COM_DET RBC[0:1] RX[0:9] 2 10 receiver REFCLK EWRAP EN_CDET [106.25 MHz] FC106 transmitter
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FC106
3
Functional Description
The FC106 provides all required signals in the 10-Bit Interface Specification for Fibre Channel. It also provides 10 pins for additional functions (these pins are marked in the following by *). The additional functions are:
* impedance control (ZC+*, ZC-*) * production test through JTAG (TCK(*)-TRSTN(*)-TMS (*)-TDI(*)-TDO (*)- TEST ENABLE (*)) * self-test of the chip (AT*) * reset pin (RS) (but note that another reset is automatically generated in the chip during
power on). In addition to implementing the Fibre Channel standard, the FC106 is adaptable through the JTAG path to the transmission of any sequence of 10-bit encoded characters at rates varying between 1 and 1.1 Gbaud.
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FC106
3.1
TCK(*) TRSTN(*) TMS(*)
Block diagram
Block diagram
JTAG CONTROL
Figure 3.1
SERIALIZER
ENC
XOR Tree transmitter
TDI(*) TDO(*) TEST ENABLE(*)
TX-
TX [0:9]
TX+
8b/10b encoder
ZC+(*)
DLL clock generator
ZC setting
RCB[0:1]
Clock Recovery AT (*) RS (*)
ZC-(*)
REFCLK
8b/10b decoder
Word Alignment
Bit Alignment rece iver
RX-
SELF TEST
ENC
RX+
DESERIALIZER
RX[0:9] EN_CDET COM_DET
(*)Test signals not included in FCS 10-bit interface EWRAP
3.2
Input latches
The transmitter accepts 10-bit wide TTL parallel data at inputs TX[0:9]. The user-provided reference clock signal REFCLK is also used as the transmit byte clock. The TX[0:9] and REFCLK signals must be properly aligned, as shown in Section 6.1: Transmit interface timing and latency on page 20.
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FC106
3.3
8bit/10bit Encoder/Decoder
In normal operation mode, the FC106 accepts 10-bit pre-encoded data, and provides to the application, 10-bit encoded data (as specified in the ANSI 10-bit Interface Specification). In addition, the FC106 contains an 8b/10b encoder/decoder, which can be inserted into the data flow. The selection of this mode is made through the JTAG path. In this mode, the FC106 accepts and delivers bytes on 9 bits (8 bits of data on TX/RX[0:7] and 1 bit on TX/ RX[8] which is used to differentiate control characters). The timings of the parallel I/O ports are identical in both modes: using the 8b/10b encoder/decoder increases the transmission latency by 2 byte clock periods (equivalent to a 4 meter increase of the cable length).
3.4
DLL clock generator
The Delay Locked Loop (DLL) block generates the internal clocks. These are required by the transmitter section to perform its function, and by the receiver block to generate the reference clocks which are used to recover the serial data input frequency. These clocks are based on the user supplied reference byte clock REFCLK. This clock is multiplied by 10 to generate the required serial output data rate. No external components are required to operate the DLL Clock Generator.
3.5
Serializer functional description and reference clock
The FC106 serializer performs the serialization of 10-bit pre-encoded parallel data at signaling rates up to 1.0625 Gb/s. System design is simplified by the integration into the chip of a block performing clock multiplication from the parallel data clock. It accepts 10-bit encoded parallel data words which are clocked into the device at 1/10 of the signaling rate. For Fibre Channel use, data should be encoded for transmission using the 8B/10B block code described in the Fibre Channel specification. The FC106 serializes the input data and transmits it at a signaling rate of 10 times the frequency of the REFCLK input. The device includes a Delay-Locked-Loop based clock multiplier that generates the 1.0625 Gbaud clocks. This DLL is fully monolithic and requires no external components. Its acquisition time, at power-up, is less than 16 microseconds. The FC106 loads parallel data on the rising edge of REFCLK. The delay through the FC106 from loading the code-group to the transmission of the first bit of the code-group on the TX+, TX- pair, is 17.4 ns with an extra 9.4 ns if the 8b10b encoding function is enabled. A loop-back-mode signal EWRAP is provided allowing internal dynamic self-test of the chip. When EWRAP is low, the output of the transmitter is sent to the TX+ and TX- output pins, and the input of the receiver is driven by the signals entered through the RX+ and RX- pins.
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FC106
When EWRAP is high, the output of the transmitter is sent directly to the input of the receiver.
3.6
Serializer latches and XOR-tree
The parallel data words TX[0:9] are individually sampled using the clocks provided by the DLL Clock Generator. The outputs of these serializer latches are merged through an Exclusive-OR tree, in order to generate the output data bit streams.
3.7
Serial input multiplexer
The Input Multiplexer supports the internal loopback of the high speed serial signal for test purposes. In normal operation, EWRAP is set low. The serial output data stream is placed at TX+/TXoutputs, and the serial data accepted at RX+/RX- is transmitted to the deserializer block. When wrap-mode is activated by setting EWRAP high, the serial data generated by the serializer block is internally wrapped to the input of the deserializer block.
3.8
Deserializer functional description
The FC106 deserializer operates at signaling rates up to 1.0625 Gb/s, as specified in the Fibre Channel standard. It extracts the clock and retimes the data from the serial bit stream. The serial bit stream should be encoded as 10-bit characters (for example the 8B/10B code for Fibre Channel) which provide a transition density greater than 10%. The retimed serial bit stream is converted into a 10-bit parallel output word. The FC106 has internal DLL based clock recovery circuit which requires no external components. When the DLL of the serializer clock multiplier is locked to the expected data rate (defined by REFCLK), the retiming acquisition time (to lock to the incoming serial data stream) is less than 3 microseconds. The FC106 provides byte and data word alignment using a comma symbol recognition mechanism. The 7-bit comma symbol is defined in Fibre Channel specification as a [0:6]= 0011111. This pattern is only contained within special characters known as K28.1, K28.5 and K28.7 defined specifically for synchronization by Fibre Channel. Serial data is received on the RX+ and RX- pins. The DLL clock recovery circuit will lock to the data stream if the clock to be recovered is within 0.01% of the expected data rate. For
10/32 September 98 Revision 1.2
FC106
example, if the REFCLK used is 106.25 MHz, then the incoming data serial signaling rate must be 1.0625 0.0001 Gb/s. The FC106 provides 2 TTL recovered clocks RBC[0] and RBC[1], which are both driven at a frequency of one twentieth of the serial signaling rate. These clocks are generated by the clock recovery DLL, which is phase locked to the serial data. RBC[1] is 180 out of phase with RBC[0]. If serial data is not present, or does not meet the required transition density or signaling rate, the RBC frequencies will be half of the expected recovered clock frequency (defined by REFCLK). This function replaces the optional LCK_REF signal that is specified in the Fibre Channel 10-bit interface. When no data is present, phase adjustments are required for switching between a locking to incoming data and locking to REFCLK. The specification on output clocks RBC[0:1] is maintained during these adjustments.The clock periods are not truncated. The serial data is retimed and deserialized. Parallel data is loaded into the output register, and therefore accessible on the output data port. For Fibre Channel use, bytes 1 and 3 of the receive data word will be accessible on the rising edge of RBC[0], and bytes 0 and 2 on the rising edge of RBC[1]. Word synchronization is enabled in the FC106 by connecting the EN_CDET pin to V dd. When EN_CDET is set high, the FC106 examines serial data for the presence of a positive disparity comma symbol (0011111). Improper alignment occurs when a comma symbol straddles a 10-bit boundary or is not aligned within the 10-bit transmission character. Proper alignment is reached by shifting the boundary of the parallel output. At power up the FC106 will not be in synchronization and data alignment is not established. The COM_DET output signal is then set low. When a comma symbol is detected, COM_DET is set high (if EN_CDET is already set high). COM_DET will go high only during a cycle in which RBC[1] is rising (see Section 6.2.2: Receive interface timing on page 23 for precise timing). Note that if EN_CDET is set low, but a comma is detected while the input stream is already word-aligned, COM_DET will be set high again.
3.9
Bit alignment
The alignment block aligns the incoming data bit stream and the reference clocks generated by the DLL Clock Generator. It compensates for clock frequency dispersions between the crystals generating the respective reference clocks REFCLK of the transmitting and receiving chips.
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FC106
3.10 Byte and word alignment
The word alignment function is performed under control of the EN_CDET signal. When EN_CDET is high, the word alignment function is operational. If an improperly aligned comma is encountered, the internal data is shifted to realign the comma character at the deserializer output (RX[0:9]). In this process, up to three characters prior to the comma character may be corrupted.
3.11 Clock recovery
The clock recovery block generates the two receiver byte clocks RBC[0:1] at half the frequency corresponding to the RX+/RX- byte data rate. These two byte clocks are 180 out of phase with each other. They are alternatively used to clock the 10-bit parallel output data.
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FC106
3.12 Serial input-output buffer
Figure 3.2 shows a simplified schematic of the serial I/O. Figure 3.2 Schematic diagram of serial I/O
Vdd Vdd
Dout-
Dout+
V ss
Vss
Transmitting Chip
TX+
Rs
Rout
TXRs
See Section 3.13 for configuration control versus line impedance
0.01F Rc
0.01F(optional)
Receiving Chip
1.5 K
RX+
RX1.5 K
Rin
1.5 K
1.5 K
TO DESERIALIZER
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FC106
3.13 I/O impedance control
The ZC block sets the internal RX+/RX- and the TX+/TX- matching impedance. Table 3.1 details the different settings. Table 3.1 ZC block settings
ZC+ Case 1: 50 line
Rout = 100 Rc = 100 R > 1.5K
ZC-
ADD Rs ADD Rc +/-1% +/-1% 100
Rs = 0
LINE = 50 External Rc
OPEN OPEN 0 or Vdd or Vdd
transmitter
Rs = 0
receiver
Case 2: 50 line
Rout = 100 Rin = 100 R > 1.5K
Rs = 0
LINE = 50 Vss No external Rc Use internal Rc
receiver
OPEN 0 or Vdd
NONE
transmitter
Rs = 0
Case 3: 75 line
Rout = 100 Rc = 150
Rs = 25
transmitter-
R > 1.5K
LINE = 75 External Rc
OPEN OPEN 25 or Vdd or Vdd
150
Rs = 25
receiver
Case 4: 75 line
Rout = 150 Rc = 150 R > 1.5K
Rs = 0
LINE = 75 External Rc
OPEN Vss or Vdd
0
150
transmitter
Rs = 0
receiver
Case 5: 75 line
Rout = 150 Rin = 150 R > 1.5K
Rs = 0
LINE = 75 Vss No external Rc Use internal Rc
receiver
Vss
0
NONE
transmitter
Rs = 0
Case 3 and 4 are identical applications: Case 3 allows better on board compatibility with other FC parts that request 25 series resistors. Exact value of Rout and Rin are detailed in Section 5.3: DC characteristics on page 18. 14/32 September 98 Revision 1.2
FC106
3.14 Self-test
The self-test block generates its own internal clock (the frequency of which can be digitally tuned through the JTAG port), and pseudo-random patterns. This data is encoded, serialized, deserialized (through the loop-back test path, or through an external connection between TX+/TX- and RX+/RX-) and decoded. The recovered data is checked; the errors and the number of transmitted bytes are internally counted. The contents of these counters are accessible through the JTAG path. This block is activated by the AT signal. In normal operation, AT is tied to Vdd and the self-test block is disabled. During production tests, AT is forced to Vss, allowing full speed dynamic tests, even at wafer level.
15/32 September 98 Revision 1.2
FC106
4
Serial I/O Electrical Model
Serial I/O electrical schematic diagram
Vdd Vss Tr R1 1pF 1pF R1 Tr = Tf = 0.2nS Vdd Tf V ss
This simplified model is given for typical board simulation, within 15% precision. The termination at the receiving end can be either internal or external, following Section 3.13. Figure 4.1
Simplified serial transmitter model
Rout
Zc = 40 Td = 0.15nS
Zc = 40 Td = 0.15nS
Simplified QFP64 package model
Your board and/or cable/connector model
0.01F(optional) Rc 0.01F(optional)
Zc = 60 Td = 0.15nS
Zc = 60 Td = 0.15nS
Simplified QFP64 package model
0.5pF Rin
0.5pF
Simplified serial receiver model
1.5K
1.5K 1.5K 1.5K TO DESERIALIZER
50 CONFIGURATI ON PARAMETER VALUES FOR TYPICAL SIMULATIO N R1 Rout Rc Rin 100 200 100 if external termination 100 if internal termination
75 CONFIGURA TION 150 300 150 if external termination 150 if internal termination
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FC106
5
5.1
Symbol Vdd V V INL INH
Electrical Specifications
Absolute maximum ratings
Absolute maximum ratings
Parameter Supply Voltage Serial signal input low level Serial signal input high level Units V V V Min 0 -0.5 Vdd+0.5 Max 4
Table 5.1
ZC+, ZC-
V
Vdd+0.5
TTL input signals TC MAX Maximum assembly temperature (for 10 seconds maximum) Storage temperature
V C C -65
5.5 260 150
Note
Stresses greater those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not guaranteed. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During overload conditions (VIN>Vdd or VIN5.2
Symbol Vdd
Operating conditions
Operating conditions
Parameter Supply Voltage Supply Ripple (DC to 3 GHz) Units V mV C mA 0 25 150 Min 3.0 Typ 3.3 Max 3.6 100 70
Table 5.2
T A IDD
Ambient temperature Supply current @ 25C, 3.3 volts with parallel outputs loaded by 10pF
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FC106
5.3
DC characteristics
DC characteristics for TX+, TX-, RX+ and RXParameter Serial output low level, terminated differentially by an external 100 resistor ( Zc+ = Zc- = "open" ) Units V Min. 0.90 Typ 1.05 Max. 1.20
The following values apply to the analog signals TX+, TX-, RX+ and RXTable 5.3
Symbol V OLS50 V OHS50 V OLS75 V OHS75 V OD50 V OD75 ROUT50 ROUT75 RIN50
Serial output high level, terminated differen- V tially by an external 100 resistor ( Zc+ = Zc- = "open" ) Serial output low level, terminated differentially by an external 150 resistor ( Zc+ = "open" - Zc- = "Vss" ) V
1.50
1.80
2.10
0.90
1.05
1.20
Serial output high level, terminated differen- V tially by an external 150 resistor ( Zc+ = "open" - Zc- = "Vss" ) Serial output peak-to-peak differential voltage, terminated differentially by an external 100 resistor ( Zc+ = Zc- = "open" ) Serial output peak-to-peak differential voltage, terminated differentially by an external 150 resistor ( Zc+ ="open" - Zc- = "Vss" ) V
1.50
1.80
2.10
1.20
1.50
1.80
V
1.20
1.50
1.80
Internal differential output impedance. When 50 line ( Zc+ = Zc- = "open" ) Internal differential output impedance. When 75 line ( Zc+ ="open" - Zc- = "Vss" ) Internal differential input impedance. When enabled for 50 line ( Zc+ = Vss / Zc- = "open" )
77 116 59
100 150 100
169 255 183
RIN75 V
Internal differential output impedance. When enabled for 75 line ( Zc+ = Zc- = Vss ) Serial input peak-to-peak differential voltage V on RX+ and RX-
95 0.2
150 -
265 -
ISWS
Note
Values above are given with normal Zc setting. In accordance with Section 3.13, it is still possible to stay with 50 internal control and connect the part to 75 impedance line by adding 25 series resistances.
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FC106
The following values apply to the logic signals. Table 5.4
Symbol V IL
DC characteristics for logic signals
Parameter Input "low" voltage level Conditions Vdd=3.3V Vdd=3.3V Vdd=3.3V Iol = 3mA Units V Min. Typ Max 0.8
V
IH
Input "high" voltage level Low level output voltage
V V
2.0
-
5.5 0.4
VOL
VOH
High level output voltage
Vdd=3.3V Ioh = 3mA
V A A
2.4
I
IL
Input low current
Vdd=max Vin=GND
125
I
IH
Input high current
Vdd=max Vin=Vdd
125
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FC106
6
6.1
Timing Specifications
Transmit interface timing and latency
Transmit interface timing and latency
All AC measurements are made from the reference voltage level of the clock (1.4 volts), to the valid input or output data levels.
Figure 6.1
REFCLK
Tref
1.4V
2.0V
TX[0:9]
VALID DATA 1 Tsu_tx
VALID DATA 2
VALID DATA 3
1.4V 0.8V
Th_tx
bit 0 of parallel input (TX0 of DATA 1)
TX+
TELA
Table 6.1
Transmit interface timing characteristics
Min 100 100 0.6 0.6 Typ Max Units MHz ppm nS nS pS % ns ns ns
Parameter Description Fref=1/Tref F tol Reference clock frequency Frequency tolerance (dispersion between REFCLK of transmitter and receiver chips) REFCLK Clock Rise Time (0.8 to 2V) REFCLK Clock Fall Time (0.8 to 2V) REFCLK Jitter REFCLK duty Cycle Data set-up to a rising edge of REFCLK Data hold after a rising edge of REFCLK Parallel data rise and fall time (10 pF load) Data Emission Latency (delay from the initial 10-bit word load to the serial transmission of bit 0)
106.25 110 + 100 2.4 2.4 40 60 3 1 REFCLK cycle + 8 ns
T r T f CLKJIT DT Tsu_tx Th_tx TX-Tr,Tf TELA
40 0 1.5 0.6 -
-
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FC106
6.2
Receive interface timing
6.2.1 Receive clock timing and latency
Figure 6.2 Receive clock timing
bit 0 of serial data
TX+
Trbc1
RBC[1]
Trbc_skew
1.4V
RBC[0]
Trbc0
1.4V
Table 6.2
Parameter Trbc0 Trbc1 Trbc_skew RBC[0,1] Tr, Tf
Receive clock timing characteristics
Description RBC[0] frequency1 RBC[1] frequency1 RBC skew Receive clock rise and fall time (10pF load) 8.9 Min Typ 53.125 53.125 2.5 9.9 Max Units MHz MHz ns ns
1. Exact frequency of RBC(0,1) depends upon the received data frequency. During byte alignment, the frequency of clocks RBC[0] and RBC[1] may vary by less than 1% of the specified typical value. The clocks are guaranteed to be glitch free.
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FC106
Figure 6.3 Receive clock latency
bit 0 of serial data 1
TX+
RBC[1]
RBC[0]
RX[0:9]
DATA 1
TRLA
Table 6.3
Parameter TRLA
Receive clock latency characteristics
Description Data Reception Latency: Serial (first bit at receiver) to 10-bit parallel output sampled by RBC[0,1]. Min Typ Max 5 RBC cycles + 4 ns Units ns
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FC106
6.2.2 Receive interface timing
Figure 6.4 Receive interface timing
RBC[0]
1.4V
RBC[1]
1.4V
Th_rx1
Tsu_rx0
2.0V
RX[0:9]
COMMA CHARACTER
VALID DATA 0.8V
Tsu_rx1
Th_rx0
2.0V
COM_DET
0.8V
Tsu_com
Th_com
Table 6.4
Parameter Tsu_rx1 Th_rx1 Tsu_rx0 Th_rx0 Tsu_com
Receive interface characteristics
Description Data valid before a rising edge of RBC[1] Data valid after a rising edge of RBC[1] Data valid before a rising edge of RBC[0] Data valid after a rising edge of RBC[0] Signal COM_DET valid before a rising edge of RBC[1] Min 3 1.5 3 1.5 3 Typ Max Units ns ns ns ns ns
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FC106
Parameter Th_com COM_DET Tr, Tf RX[0:9]
Description Signal COM_DET valid after a rising edge of RBC[1] COM_DET rise and fall time (10pF load) RX(n) rise and fall time (10pF load)
Min 1.5
Typ 2.5 2.5
Max -
Units ns ns ns
6.3
Serial Input/output AC characteristics
Serial I/O AC characteristics
Description Min Typ 200 200 Max 25 Units ps ps ps
Table 6.5
Parameter t t t RS FS SK
Serial output rise time, terminated by the FC106 receiver (20%-80%) Serial output fall time, terminated by the FC106 receiver (20%-80%) Differential skew between TX+ and TX-, terminated by the FC106 receiver
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FC106
7
7.1
Pin AT*
FC106 Pin Description
Pin summary
Pin summary
Level CMOS Description This signal places the chip in a self-test mode when tied low. It should be tied to Vdd in any other state of the chip, as specified in the 10-Bit Interface Specification standard. COM_DET is an indication that the data byte (byte 0 of word 0) associated with the current RBC[1] contains a valid comma symbol. EN_CDET enables the chip to perform the byte alignment function on comma symbols. When EN_CDET is high, the byte alignment function is operational. When EN_CDET is low, the current byte alignment is maintained. EWRAP causes the chip to internally loop serialized transmit data to the deserializer. EWRAP is active on high level. RBC[0] is the 53.125 MHz receive byte clock that the protocol device will use to register the bytes 1 and 3 of the received data word. This clock may be stretched during byte alignment (never slivered or truncated). RBC[1] is the 53.125 MHz receive byte clock that the protocol device will use to register the bytes 0 and 2 of the received data word. RBC[1] is 180 out of phase with RBC[0]. This clock may be stretched during byte alignment (never slivered or truncated). REFCLK is the 106.25 MHz reference clock. The frequency tolerance for this clock should meet ANSI X3.230-1994 Fibre Channel FC-PH specifications for a Fibre Channel use. See Section 6.1:Transmit interface timing and latency on page 20. RX+ and RX- are the differential inputs for serialized data on the receiver. RX[0:9] is the 10-bit parallel received data presented by the chip to the upper layer for further processing. The received data byte 0 containing the comma symbol will be byte aligned to RBC[1], i.e. byte 0 is in phase with RBC[1]. The order of reception on the serial input is RX[0] first, followed by RX[1] through to RX[9]. These signals are compliant to the JTAG specification.
Table 7.1
COM_DET EN_CDET
CMOS CMOS
EWRAP RBC[0]
CMOS CMOS
RBC[1]
CMOS
REFCLK
CMOS
RX+, RXRX[0:9]
Special CMOS
TCK*, TRSTN*, TMS*, TDI*, TDO* TEST ENABLE* TX+, TX-
CMOS
CMOS Special
Used during ATPG test, connected at V in normal operation. ss TX+ and TX- are the differential outputs for serialized data on the transmitter.
25/32 September 98 Revision 1.2
FC106
Pin TX[0:9] Level CMOS Description TX[0:9] is the 10-bit parallel transmit data presented to the chip for serialization and transmission onto the media. The order of transmission is TX[0] through to TX[9]. These pins are used to control the input and output impedance in accordance with the configuration outlined in Section 3.13:I/O impedance control on page 14.
ZC+1, ZC-*
CMOS
1. indicates signals that are not included in the Fibre Channel 10-Bit Interface Specification.
7.2
Pin functions
Pin functions
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 I/O I I I I I I I I I I (I) pull up/ Description in standard running conditions down pd pd pd pd pd pd pd pd pd pd pd Ground Pin Bit 0 of parallel transmit data (first bit sent) Bit 1 of parallel transmit data Bit 2 of parallel transmit data Power Pin Bit 3 of parallel transmit data Bit 4 of parallel transmit data Bit 5 of parallel transmit data Bit 6 of parallel transmit data Power Pin Bit 7 of parallel transmit data Bit 8 of parallel transmit data Bit 9 of parallel transmit data (last bit sent) Ground Pin Must be tied to GND during normal operation. External During power up, an internal circuit will reset automatically reset the chip. Nevertheless RS allows a forced reset (when high), during normal operation. Not connected Not connected JTAG scan in Test clock pin for JTAG TEST pins
Table 7.2
Pin Name Vss TX[0] TX[1] TX[2] Vdd TX[3] TX[4] TX[5] TX[6] Vdd TX[7] TX[8] TX[9] Vss Vss/RS
NC/TDI NC/TCK
16 17
(I) (I)
pd pd
26/32 September 98 Revision 1.2
FC106
pull up/ Description in standard running conditions down pu pd pu Must be tied to Vdd. When tied to Vdd, causes the chip to internally loop serialized transmit data to the deserializer. Must be tied to Vdd. Test mode select for JTAG TEST pins Reset pin for JTAG
Pin Name Vdd/TRSTN EWRAP Vdd/TMS
Pin # 18 19 20
I/O (I) I (I)
Vss REFCLK Vdd EN_CDET TEST ENABLE NC/TDO NC Vdd/AT
21 22 23 24 25 26 27 28
I I I I (O) (I)
pd pu pd pu
Ground Pin Reference clock frequency 106.25 MHz Power Pin Enables the chip to perform the byte alignment function when HIGH. Must be tied to GND. Not connected Not connected Must be tied to Vdd. Tie to Vdd for AT PG JTAG scan out Places the chip in auto test mode when LOW.
Vdd RBC[1] RBC[0] Vss Vss RX[9] RX[8] RX[7] Vdd RX[6] RX[5] RX[4] RX[3] Vdd 27/32 September 98
29 30 31 32 33 34 35 36 37 38 39 40 41 42
O O O O O O O O O -
Power Pin Receive byte clock used by the protocol to register byte 0 and 2 of the receive parallel data. Receive byte clock used by the protocol to register byte 1 and 3 of the receive parallel data. Ground Pin Ground Pin Bit 9 of parallel receive data (last bit received) Bit 8 of parallel receive data Bit 7 of parallel receive data Power Pin Bit 6 of parallel receive data Bit 5 of parallel receive data Bit 4 of parallel receive data Bit 3 of parallel receive data Power Pin
Revision 1.2
FC106
pull up/ Description in standard running conditions down Bit 2 of parallel receive data Bit 1 of parallel receive data Bit 0 of parallel receive data (first bit received). Ground Pin Goes high when detecting a comma symbol. Data byte associated with RBC[1] contains valid comma symbol. Used for impedance adaptation (see Section 3.13) Used for impedance adaptation (see Section 3.13) Power Pin Ground Pin One of the differential inputs for serialized data on the receiver. Serial input frequency must be 1.0625 0.0001 Gb/s. Power Pin One of the differential inputs for serialized data on the receiver. Serial input frequency must be 1.0625 0.0001 Gb/s. Power Pin Ground Pin Power Pin Ground Pin Power Pin Power Pin One of the differential outputs for serialized data on the transmitter. Serial output rate depends on REFCLK. One of the differential outputs for serialized data on the transmitter. Serial output rate depends on REFCLK. Power Pin Not connected TEST pins
Pin Name RX[2] RX[1] RX[0] Vss COM_DET
Pin # 43 44 45 46 47
I/O O O O O
ZCZC+ Vdd Vss RX-
48 49 50 51 52
1 1 I
pu pu -
Vdd RX+
53 54
I
-
Vdd Vss Vdd Vss Vdd Vdd TX-
55 56 57 58 59 60 61
O
-
TX+
62
O
-
Vdd NC
63 64
-
-
28/32 September 98 Revision 1.2
FC106
8
Package Specifications
The FC106 is available in two sizes of 64-pin plastic quad flat-pack: the FC106/14 measures 14x14 mm and the FC106/10 measures 10x10 mm.
8.1
FC106 64-pin PQFP pinout
Pinout for 64-pin PQFP (both 14x14 mm and 10x10 mm sizes)
Figure 8.1
RX+
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49 48 47 46 45 44 43 42 41 40 39 38 37
Vss TX0 TX1 TX2 Vdd TX3 TX4 TX5 TX6 Vdd TX7 TX8 TX9 Vss Vss NC
ZC+
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
TX+
Vss
Vss
Vss
RX-
TX-
NC
1 2 3 4 5 6 7 8 9 10 11 12 AT (for testing purposes) 13 14 15
ZCCOM_DET Vss RX0 RX1 RX2 Vdd RX3 RX4 RX5 RX6 Vdd RX7 RX8 RX9 Vss
TMS
TDO
TCK
16 TDI
TEST ENABLE
RS (test mode)
TRSTN
JTAG PINS
FC 106
36 35 34 33 29 30 31 32
17
18
19
20
21
22
23
24
25
26
27
28
Vdd
Vdd
Vdd
Vdd
EN_CDET
REFCLK
Vdd
NC
NC
RBC[1]
Vss
Vss
EWRAP
NC+
29/32 September 98 Revision 1.2
RBC[0]
Vss
FC106
8.2
FC106 64-pin Quad Flat-pack package dimensions
Data for 64-pin 14x14 mm PQFP
mm inch MAX. 2.35 0.25 2.10 0.40 0.17 17.45 14.10 17.45 14.10 0-7 0.78 0.88
DD D1 D1 A A D2 D3
A1 A1 A2 A2
8.2.1 FC106/14: 14x14 mm package dimensions
Figure 8.2
DIM MIN. A A1 A2 b c D D1 D2 e E E1 E2 1.95 0.30 16.95 13.90 16.95 13.90 TYP. 2.00 0.35 17.20 14.00 12.00 0.80 17.20 14.00 12.00 MIN. 0.077 0.012 0.667 0.547 0.667 0.547 0.031 TYP. 0.079 0.014 0.677 0.551 0.472 0.031 0.677 0.550 0.472 0.035 MAX. 0.093 0.010 0.083 0.016 0.067 0.687 0.555 0.687 0.555 0.041
Thermal resistance = 45C/W (still air)
PQFP64 Body: 14 x 14 x 2.0 mm Footprint: 3.20 mm
L
1.03
48 48 49 49
33 33 32 32
0.10mm 0.1mm Seating Plane SeatingPlane
b
B E3 E1 E B
b E2 E1 E
64 64 1 1
e e
17 17
16 16
c C
L1
L
L
K
PQFP64 PQFP64
30/32 September 98 Revision 1.2
FC106
8.2.2 FC106/10: 10x10 mm package dimensions
Figure 8.3
DIM MIN. A A1 A2 b c D D1 D2 e E E1 E2 0.25 1.95 0.17 12.95 9.90 12.95 9.90 0.78 TYP. 2.00 0.22 13.20 10.00 7.50 0.50 13.20 10.00 7.50 0.88 MAX. 2.45 0.50 2.10 0.27 0.17 13.45 10.10 13.45 10.10 1.03 MIN. 0.010 0.077 0.007 0.510 0.390 0.510 0.390 0.031 TYP. 0.079 0.009 0.520 0.394 0.295 0.020 0.520 0.394 0.295 0.035 MAX. 0.097 0.020 0.083 0.011 0.067 0.530 0.398 0.530 0.398 0.041
Thermal resistance = 45C/W (still air)
Data for 64-pin 10x10 mm PQFP
mm inch
PQFP64 Body: 10 x 10 x 2.0 mm Footprint: 3.20mm
L
0-7
DD D1 D1 A A D2 D3
A1 A1 A2 A2
48 48 49 49
33 33 32 32
0.10mm 0.1mm Seating Plane SeatingPlane
b
B E3
E2
E1
E1
E
64 64 1 1
e e
17 17
16 16
E
B
b
c C
L1
L
L
K
PQFP64 PQFP64
31/32 September 98 Revision 1.2
FC106
Information furnished is belived to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. This circuit uses patents licensed by BULL S.A.. The ST logo is a trademark of STMicroelectronics. (c) 1998 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - United Kingdom - U.S.A.
32/32 September 98
Document Number 42 1686 Revision 1.2 32

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